Semiconductor-on-insulator (soi) substrates and semiconductor devices using void spaces

ABSTRACT

An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of application Ser. No. 10/972,972,filed Oct. 25, 2004, entitled Methods of FabricatingSemiconductor-on-Insulator (SOI) Substrates and Semiconductor DevicesUsing Sacrificial Layers and Void Spaces, and claims the benefit ofpriority Korea Patent Application No. 2003-85237 filed on Nov. 27, 2003,the disclosures of both of which are hereby incorporated herein byreference in their entirety as if set forth fully herein.

FIELD OF THE INVENTION

The present invention relates to fabricating semiconductor devices and,more particularly, to methods for forming Semiconductor-on-Insulator(SOI) substrates and devices, and semiconductor devices fabricatedthereby.

BACKGROUND OF THE INVENTION

As the integration density of integrated circuit semiconductor devicescontinues to increase, it may be increasingly difficult to isolatemicroelectronic devices such as transistors, from one another, when theyare formed in bulk semiconductor substrates such as bulk siliconsemiconductor substrates. Semiconductor-on-Insulator (SOI) technologyhas been proposed as an alternative to bulk semiconductor technology. InSOI technology a thin semiconductor layer is formed on a substrate,which may be a semiconductor substrate, with an intervening insulatorlayer therebetween. Microelectronic devices such as transistors areformed in the thin semiconductor layer, which may be referred to as anactive semiconductor layer or an active layer. Often the activesemiconductor layer comprises a thin monocrystalline silicon layer, theinsulating layer comprises a silicon oxide layer, and the substrate is amonocrystalline silicon substrate. However, other substrates, insulatinglayers and active semiconductor layers may be used.

Hereinafter, conventional methods for fabricating an SOI substrate willbe described with reference to FIGS. 1A to 1F.

Referring to FIGS. 1A and 1B, a base wafer W1 and a bonding wafer W2 areprepared. The base wafer W1 includes a silicon substrate 10 and anoxidation layer 11 formed on the silicon substrate 10. The bonding waferW2 includes a silicon substrate 20, and an isolation layer 21 and asilicon layer 22 stacked on the silicon substrate 20 in sequence. Theisolation layer 21 may be formed of various materials. For example, theisolation layer 21 may be formed of a porous silicon layer or anion-implanted silicon layer.

Referring to FIG. 1C, thermal treatment is performed while the oxidationlayer 11 of the base wafer W1 and the silicon layer 22 of the bondingwafer W2 are contacted to each other to thereby bond the base wafer W1and the bonding wafer W2.

Referring to FIG. 1D, the silicon substrate 20 of the bonding wafer W2is isolated from the base wafer W1 by removing the isolation layer 21,and the surface of the silicon layer 22 is polished.

In accordance with the above-mentioned procedure, an SOI substrateincluding the silicon substrate 10, the oxidation layer 11, and thesilicon layer 22, is prepared. The silicon layer 22 acts as an activesemiconductor layer where active elements such as MOS transistors areformed. Thus, the thickness of the silicon layer 22 affects theperformance of the MOS transistors. For example, the thickness of thesilicon layer 22 may be reduced in order to potentially improve shortchannel effects of the MOS transistors.

Referring to FIG. 1E, the silicon layer 22 is thermally oxidized tothereby form a thermal oxidation layer 13 on the surface of the siliconlayer 22. As a result, the thickness of the silicon layer 22 is reducedso that a silicon layer 22 a thinner than the silicon layer 22 can beobtained.

Referring to FIG. 1F, the thermal oxidation layer 13 is removed toexpose the silicon layer 22 a. The final thickness of the silicon layer22 a may be determined by the thermal oxidation processing time or thenumber of the repeating thermal oxidation process.

The above-mentioned conventional method for fabricating the SOIsubstrate adjusts the thickness of the silicon layer 22 by forming andremoving the thermal oxidation layer on the surface of the silicon layer22, so that the thickness may be difficult to control, and in addition,the silicon layer may be largely consumed. Thus, the method may not bedesirable for mass production because the manufacturing cost mayincrease.

Moreover, in the conventional method for fabricating the SOI substrate,in order to perform processes of reducing the isolation layer 21 andpolishing the silicon layer 22, the silicon layer 22 should be formed tohave at least a minimum thickness. However, a wafer having a largediameter may have a large temperature difference according to the areaof its surface, a high degree of bending, and/or a uniformity differencewhen polishing, oxidation and/or etching processes are performed,compared to a wafer having a small diameter. In particular, the thinnerthe silicon layer, the greater the uniformity variation may become, sothat the thickness difference over the wafer may be excessive. Thethickness difference over the area of the wafer may still be presentafter the polishing and oxidation processes of the silicon layer 22, sothat it may become more difficult to obtain the thin and uniform siliconlayer 22 a.

SUMMARY OF THE INVENTION

Some embodiments of the present invention fabricate an SOI substrate byproviding a substrate having a sacrificial layer thereon, an activesemiconductor layer on the sacrificial layer remote from the substrateand a supporting layer that extends along at least two sides of theactive semiconductor layer and the sacrificial layer and onto thesubstrate, and that exposes at least one side of the sacrificial layer.At least some of the sacrificial layer is etched through the at leastone side thereof that is exposed by the supporting layer to form a voidspace between the substrate and the active semiconductor layer, suchthat the active semiconductor layer is supported in spaced-apartrelation from the substrate by the supporting layer. In someembodiments, the void space may be at least partially filled with aninsulator lining.

Other embodiments of the present invention fabricate an SOI substrate byforming a stack pattern including a sacrificial layer and an activesemiconductor layer, which can be epitaxially grown on a substrate suchas a semiconductor substrate, in sequence. The sacrificial layer isformed of a material having etch selectivity with respect to thesubstrate and the active semiconductor layer. A supporting pattern isformed on the semiconductor substrate to contact at least two sides ofthe stack pattern. At least one side of the active layer and thesacrificial layer of the stack pattern are exposed. The sacrificiallayer is then selectively removed through the at least one side thereofthat is exposed to form a void space between the substrate and theactive semiconductor layer.

Methods for fabricating an SOI substrate in accordance with otherembodiments of the present invention comprise forming a supportingpattern on a substrate. A sacrificial layer and an active semiconductorlayer are formed, which may be epitaxially grown on the exposed portionof the substrate such that at least two sides thereof are in contactwith the supporting pattern and at least one side of the sacrificiallayer and the active semiconductor layer are exposed. The sacrificiallayer is formed of a material having etch selectivity with respect tothe substrate and the active semiconductor layer. The sacrificial layerand the active semiconductor layer that are not in contact with thesupporting pattern are selectively removed to expose other sides of thesacrificial layer and the active semiconductor layer. The sacrificiallayer is selectively removed to form a void space between the substrateand the active semiconductor layer.

Other embodiments of the present invention provide methods forfabricating semiconductor devices using an SOI substrate. Theseembodiments comprise epitaxially growing a sacrificial layer and anactive semiconductor layer on a substrate in sequence. The sacrificiallayer is formed of a material having etch selectivity with respect tothe substrate and the active semiconductor layer. The activesemiconductor layer and the sacrificial layer are patterned to exposeportions of the substrate in a device isolation region. A first deviceisolation layer is formed on the exposed substrate to contact at leasttwo sides of the patterned sacrificial layer and active semiconductorlayer. At least one of the sides of the sacrificial layer and the activesemiconductor layer that are not covered with the first device isolationlayer are exposed. The sacrificial layer is selectively removed to forma void space between the substrate and the active semiconductor layer.In this case, the first device isolation layer is used as a supportinglayer of the active layer. A second device isolation layer is thenformed to cover the exposed sides of the void space and the activesemiconductor layer. A gate electrode is then formed on the activelayer.

Methods for fabricating a semiconductor device using an SOI substrate inaccordance with embodiments of the present invention comprise forming aninsulating layer or a device isolation region on a substrate thatexposes a portion of the substrate. A sacrificial layer and an activesemiconductor layer, of which at least two sides are in contact with theinsulating layer, are formed on the exposed substrate in sequence afterthe insulating layer is formed. The sacrificial layer is formed of amaterial having etch selectivity with respect to the substrate and theactive semiconductor layer. The insulating layer is patterned to form afirst device isolation layer, which covers at least two sides of thesacrificial layer and the active semiconductor layer and that exposes atleast one side of the sacrificial layer and the active semiconductorlayer. The sacrificial layer is selectively removed to form a void spacebetween the semiconductor substrate and the active layer, and the firstdevice isolation layer is used as a supporting layer of the activelayer. A second device isolation layer is then formed to cover the atleast one exposed side of the active semiconductor layer and void space.A gate electrode is then formed on the active layer.

Methods for fabricating semiconductor devices in accordance with otherembodiments of the present invention form a first device isolation layerthat covers portions of a device isolation region on a substrate. Asacrificial layer and an active semiconductor layer, the sides of whichare in contact with the first device isolation layer, are epitaxiallygrown on the exposed semiconductor substrate in sequence after the firstdevice isolation layer is formed. The sacrificial layer is formed of amaterial having etch selectivity with respect to the semiconductorsubstrate and the active semiconductor layer. The active semiconductorlayer and the sacrificial layer that are not in contact with the firstdevice isolation layer are selectively etched to expose at least oneother side of the sacrificial layer and the active layer. Thesacrificial layer is selectively removed to form a void space betweenthe substrate and the active semiconductor layer. In this case, thefirst device isolation layer is used as a supporting layer of the activelayer. A second device isolation layer is then formed to cover theexposed sides of the active semiconductor layer and the void space. Agate electrode is then formed on the active layer.

Embodiments of the present invention also can provide a semiconductordevice formed on an SOI substrate. The semiconductor device comprises asemiconductor substrate, a device isolation layer on the semiconductorsubstrate, and an active semiconductor layer supported by the deviceisolation layer and spaced from the semiconductor substrate by a voidspace therebetween. The active layer may have a lattice constant closeto that of the semiconductor substrate.

The semiconductor device may further comprise a gate electrode formed onthe active layer. The gate electrode may cover sides of the activelayer. In addition, the gate electrode may cover the upper surface ofthe active layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F show cross-sectional views for explaining a method forfabricating an SOI substrate in accordance with the prior art.

FIGS. 2A to 2F show perspective views for explaining methods forfabricating SOI substrates in accordance with embodiments of the presentinvention.

FIGS. 3A to 3F show vertical cross-sectional views taken along line I ofFIGS. 2A to 2F.

FIGS. 4A to 4F show vertical cross-sectional views taken along line IIof FIGS. 2A to 2F.

FIG. 5 shows cross-sectional views for explaining a method forfabricating an SOI substrate in accordance with other embodiments of thepresent invention.

FIGS. 6A to 6F show perspective views for explaining methods forfabricating SOI substrates in accordance with other embodiments of thepresent invention.

FIGS. 7A to 7F show vertical cross-sectional views taken along line IIIof FIGS. 6A to 6F.

FIGS. 8A to 8E show vertical cross-sectional views taken along line IVof FIGS. 6A, 6C, 6D, 6E and 6F, respectively.

FIG. 9A shows a plan view for explaining methods for fabricatingsemiconductor devices in accordance with other embodiments of thepresent invention.

FIGS. 9B and 9C show vertical cross-sectional views taken along lines Vand VI of FIG. 9A, respectively.

FIG. 10 shows a cross-sectional view for explaining methods forfabricating semiconductor devices in accordance with other embodimentsof the present invention.

FIGS. 11A to 11D show plan views for explaining methods for fabricatingsemiconductor devices in accordance with other embodiments of thepresent invention.

FIGS. 12A to 12E show vertical cross-sectional views taken along lineVII of FIGS. 11A, 11B, 11B, 11C, and 11D, respectively.

FIGS. 13A to 13E show vertical cross-sectional views taken along lineVIII of FIGS. 11A, 11B, 11B, 11C, and 11D, respectively.

FIGS. 14A and 14B show plan views for explaining methods for fabricatingsemiconductor devices in accordance with other embodiments of thepresent invention.

FIGS. 15A and 15B show vertical cross-sectional views taken along lineVII of FIGS. 14A and 14B, respectively.

FIGS. 16A and 16B show vertical cross-sectional views taken along lineVII of FIGS. 14A and 14B, respectively.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the size and relative sizes of layers and regions may beexaggerated for clarity. It will be understood that when an element orlayer is referred to as being “on” another element or layer, it can bedirectly on the other element or layer or intervening elements or layersmay be present. In contrast, when an element is referred to as being“directly on” another element or layer, there are no interveningelements or layers present, Like numbers refer to like elementsthroughout. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in the Figures is turned over, elements describedas being on the “lower” side of other elements would then be oriented on“upper” sides of the other elements. The exemplary term “lower”, cantherefore, encompass both an orientation of “lower” and “upper,”depending on the particular orientation of the figure. Similarly, if thedevice in one of the figures is turned over, elements described as“below” or “beneath” other elements would then be oriented “above” theother elements. The exemplary terms “below” or “beneath” can, therefore,encompass both an orientation of above and below.

Embodiments of the present invention are described herein with referenceto cross-sectional and/or other views that are schematic illustrationsof idealized embodiments of the present invention. As such, variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments of the present invention should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, a grown or deposited region illustrated as apolygon will, typically, have rounded or curved features and/or agradient of concentrations at its edges with another region rather thana discrete change from a first region to a second region of differentcomposition. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the preciseshape of a region of a device and are not intended to limit the scope ofthe present invention.

FIGS. 2A to 2F show perspective views for explaining methods forfabricating an SOI substrate in accordance with embodiments of thepresent invention. In addition, FIGS. 3A to 3F show verticalcross-sectional views taken along line I of FIGS. 2A to 2F, and FIGS. 4Ato 4F show vertical cross-sectional views taken along line II of FIGS.2A to 2F.

Referring to FIGS. 2A, 3A, and 4A, a sacrificial layer 110 and an activesemiconductor layer, also referred to herein simply as an active layer,120, are sequentially formed on a substrate 100, which may be asemiconductor substrate such as a monocrystalline Si substrate. In someembodiments the sacrificial layer 110 and the active layer 120 areformed by an epitaxial growth method capable of adjusting theirthickness. In some embodiments, the sacrificial layer 110 is formed of amaterial layer having etch selectivity with respect to the active layer120 and having a lattice constant close to that of the active layer 120.For example, when the active layer 120 comprises an epitaxial Si layer,the sacrificial layer 110 may comprise an epitaxial SiGe layer.

The sacrificial layer 110 and the active layer 120 may be formed byvarious epitaxial growth methods. For example, a chemical vapordeposition (CVD) method or a Molecular Beam Epitaxy method may beemployed. A furnace type device may be used as a deposition device forforming the sacrificial layer 110.

Silicon source gas such as SiH₄, SiH₂Cl₂, SiCl₄ and/or Si₂H₆ and/orgermanium source gas such as GeH₄ may be used for growing thesacrificial layer 110. The source gas such as SiH₄, SiH₂Cl₂, SiCl₄and/or Si₂H₆ may be used for growing the active layer 120.

Referring to FIGS. 2B, 3B, and 4B, a silicon nitride layer 140 and a padoxidation layer 130 are formed on the active layer 121 to cover anactive region X. The active layer 120 and the sacrificial layer 110 arethen patterned to form a patterned active layer 121 and a patternedsacrificial layer 111. A stack pattern S is formed on the substrate 100,wherein the stack pattern S comprises the silicon nitride layer 140, thepad oxidation layer 130, the active layer 121 and the sacrificial layer111. As the stack pattern S is formed, the substrate 100 of deviceisolation regions I1 and I2 surrounding the active region X is exposed.Moreover, after forming the active layer 121 and the sacrificial layer111, some portions of the substrate 100 may be etched.

Referring to FIGS. 2C, 3C, and 4C, an insulating layer 150 is formed toact as a supporting layer on the substrate 100 of the device isolationregions I1 and I2. The insulating layer 150 surrounds sides of theactive layer 121 and the sacrificial layer 111. The insulating layer 150may be a single layer or a stacked layer comprising two or more kinds ofinsulating layers. The stacked layer may include an oxidation layer anda nitride layer. Furthermore, when the insulating layer 150 is formed ofthe oxidation layer, a chemical mechanical polishing or etchback processmay be performed after performing thermal oxidation and oxidation layerdeposition processes in sequence.

Moreover, when some portions of the substrate 100 are etched afterforming the active layer 121 and the sacrificial layer 111 in accordancewith the above-mentioned process, the portions of the semiconductorsubstrate 100 may also be in contact with the insulating layer 150.

Referring to FIGS. 2D, 3D, and 4D, a mask 160 is formed to cover theinsulating layer 150 of the device isolation region I1. The insulatinglayer 150 of the device isolation region I2 is then etched to expose atleast one side of the silicon nitride layer 140, the pad oxidation layer130, the active layer 121 and the sacrificial layer 111, which aredisposed at a boundary between the active region X and the deviceisolation region I2. Thus, insulating layer patterns 151 and 152,obtained by patterning the insulating layer 150, are formed in thedevice isolation regions I1 and I2, respectively. The insulating layerpattern 151 may form a first device isolation layer.

The insulating layer pattern 151 may have the same height as the siliconnitride layer 140, and the insulating layer pattern 152 may have thesame height as the substrate 100. Moreover, the insulating layer pattern152 should not be formed by completely removing the insulating layer 150of the device isolation region I2.

Next, the sacrificial layer 111 is removed to form a void space Abetween the semiconductor substrate 100 and the active layer 121. Thevoid space A may act as an insulating layer. The insulating layerpattern 151 may act as a supporting layer for preventing collapse of thesilicon nitride layer 140, the pad oxidation 130, and the active layer121 when removing the sacrificial layer 111.

The sacrificial layer 111 may be removed by a wet etch or dry etchprocess. The sacrificial layer 111 may be etched under a conditionhaving etch selectivity of 300 or more with respect to the semiconductorsubstrate 100 and the active layer 121. When the semiconductor substrate100, the active layer 121 and the sacrificial layer 111 are formed ofsilicon, an epitaxial SiGe layer and an epitaxial Si layer,respectively, in accordance with some embodiments of the presentinvention, a mixed solution of H₂O, HNO₃, HF, and CH₃COOH may be used asan etchant to remove the sacrificial layer 111.

Referring to FIGS. 2E, 3E, and 4E, the mask 160 is removed, and aninsulating layer 170 is formed on the insulating layer pattern 152 ofthe device isolation region I2, which becomes a second device isolationlayer. The insulating layer 170 may be formed by the same method as theinsulating layer 150. As the insulating layer 170 is formed, the sidesof the silicon nitride layer 140, the pad oxidation layer 130, and theactive layer 121 that have been exposed, are covered by the insulatinglayer 170. The insulating layer 170 may also act as a supporting layerfor preventing possible collapse of the active layer 121. Thus, theactive layer 121 defining the active region X is surrounded by theinsulating layer 170 formed as the second device isolation layer, andthe insulating layer pattern 151 formed as the first device isolationlayer.

In addition, as shown in FIGS. 3E and 4E, the void space A may be atleast partially filled with an insulating layer 171 formed between thesemiconductor substrate 100 and the active layer 121 during a process offorming the insulating layer 170. These insulating layers 170 and 171may be a single layer or a stacked layer comprising two or more kinds ofinsulating layers. The stacked layer may include an oxide layer and anitride layer. When the insulating layer 171 is formed of an oxidelayer, a lower surface of the active layer 121 and some portions of thesemiconductor substrate 100 may be consumed to thereby reduce thethickness of the active layer 121 and the substrate 100.

Moreover, the insulating layer 171 may be formed so that the void spaceA remains and acts as an insulating layer. Alternatively, the void spaceA may not be completely filled with the insulating layer so that thermaloxidation layers are formed on an upper surface of the semiconductorsubstrate 100 and on the lower surface of the active layer 121 tothereby surround upper and lower portions of the void space A with thethermal oxidation layers. In other embodiments of the present inventionto be described later, a method for leaving the void space A residualand a method for forming the thermal oxidation layers will be described.

Referring to FIGS. 2F, 3F, and 4F, the silicon nitride layer 140 and thepad oxidation layer 130 are removed to expose the upper surface of theactive layer 121. Thus, an SOI substrate including the semiconductorsubstrate 100, the insulating layer 171, and the active layer 121 iscompleted. The process of patterning the sacrificial layer and theactive layer may be omitted in the above-mentioned embodiments of thepresent invention. In other words, in order to obtain the structureshown in FIGS. 2C, 3C, and 4C, a conventional STI (shallow trenchisolation) technique may be employed to form the insulating layer 150 onthe substrate 100 of the device isolation regions I1 and I2. Thesacrificial layer 111 and the active layer 121 are then epitaxiallygrown in sequence on the exposed substrate 100 after forming theinsulating layer 150 to thereby contact a side of the insulating layer150 with the sides of the sacrificial layer 110 and the active layer120. Next, the pad oxidation layer 130 and the silicon nitride layer 140may be formed as a passivation layer on the active layer 120. Processesas shown in FIGS. 2D to 2F are then performed.

In accordance with the above-mentioned embodiments of the presentinvention, processes of bonding, isolating, polishing a wafer, and thelike may be omitted. Therefore, the active layer may be grown with aminimum thickness and can be controlled from being consumed. Inaddition, it may not be necessary to form a thick active layer so thatan active layer having a uniform thickness can be formed on a wafer of alarge diameter.

Moreover, when the active layer is formed to have a thickness thatexceeds a desired thickness, the thickness of the active layer may bereduced by repeatedly forming and removing a thermal oxidation layer.Alternatively, the thickness of the active layer may be reduced byperforming an etching process.

Hereinafter, methods for reducing the thickness of the active layerusing processes of forming and removing a thermal oxidation layer willbe described with reference to FIGS. 5A to 5C.

Referring to FIG. 5A, an SOI substrate fabricated by one or more of theabove-mentioned embodiments is prepared. In particular, FIG. 5A shows anSON (silicon-on-nothing) substrate having the void space A between theactive layer 121 and the semiconductor substrate 100, which is one typeof SOI substrate.

Referring to FIG. 5B, a thermal oxidation layer 173 is formed on theactive layer 121. As the thermal oxidation layer 173 is formed, somesurfaces of the active layer 121 are consumed to thereby obtain athinner active layer 122.

Referring to FIG. 5C, the thermal oxidation layer 173 is removed toexpose the active layer 122. In this case, the insulating layer 170 maybe removed up to a height of the active layer 122.

In the above process, a desired thickness of the active layer 122 may beobtained by adjusting the number of times and/or the time for formationof the thermal oxidation layer 173.

FIGS. 6A to 6F show perspective views for explaining methods forfabricating SOI substrates in accordance with other embodiments of thepresent invention. In addition, FIGS. 7A to 7F show verticalcross-sectional views taken along line III of FIGS. 6A to 6F, and FIGS.8A to 8E show vertical cross-sectional views taken along line IV ofFIGS. 6A, 6C, 6D, 6E and 6F, respectively.

Referring to FIGS. 6A, 7A, and 8A, a stack pattern S is formed on asubstrate 200 such as a semiconductor substrate, wherein the stackpattern S comprises a silicon nitride layer 240, a pad oxidation layer230, an active layer 220 and a sacrificial layer 210. The stack patternS covers the substrate 200 on an active region X and a device isolationregion I1. As the stack pattern S is formed, a surface of the substrate200 on a device isolation region I2 is exposed. Moreover, after formingthe stack pattern S, some portions of the substrate 200 may be etched.

Referring to FIGS. 6B and 7B, an insulating layer 250 is formed as afirst device isolation layer on the substrate 200 of the deviceisolation region I1. Thus, a side of the stack pattern S formed on aboundary between the active region X and the device isolation region I1,comes in contact with the insulating layer 250.

Referring to FIGS. 6C, 7C, and 8B, a mask 260 is formed to cover theactive region X and the insulating layer 250 in contact with the activeregion X. The silicon nitride layer 240, the pad oxidation layer 230,the active layer 220 and the sacrificial layer 210 are then patterned.Thus, at least one side of the silicon nitride layer 240, the padoxidation layer 230, the active layer 220 and the sacrificial layer 210,which have been disposed at a boundary between the active region X andthe device isolation region I2, is exposed. Moreover, while patterningthe active layer 220 and the sacrificial layer 210, some portions of thesubstrate 200 may be etched as shown in FIGS. 7C and 8B.

Referring to FIGS. 6D, 7D, and 8C, the sacrificial layer 210 is removedto form a void space A between the substrate 200 and the active layer220. In this case, the insulating layer 250 acts as a supporting layerthat can prevent collapse of the silicon nitride layer 240, the padoxidation layer 230, and the active layer 220.

Referring to FIGS. 6E, 7E, and 8D, the mask 260 is removed and aninsulating layer 270 is formed as a second device isolation layer on thesubstrate 200 on the device isolation region I2. Thus, sides of thesilicon nitride layer 240, the pad oxidation layer 230, the active layer220, and the void space A are covered with the insulating layer 270.Moreover, the active layer 220 forming the active region X is surroundedby the insulating layer 250 formed as the first device isolation layer,and the insulating layer 270 formed as the second device isolationlayer. To leave the void space A residual, the insulating layer 270should not be formed in the void space during the process of forming theinsulating layer 270. Thus, the insulating layer 270 may be formed by anevaporation method. In addition, in order to enhance directionality of adeposition source, the insulating layer 270 may be formed under a highvacuum condition of 10-6 Torr or less.

In the meantime, a thermal oxidation layer 271 and a thermal oxidationlayer 272 may be formed on an upper surface of the semiconductorsubstrate 200 and a lower surface of the active layer 220, respectivelyafter forming the void space A. Thus, the thermal oxidation layer 272that provides an insulating layer, and the active layer 220 thatprovides an Si epitaxial layer, are stacked on the void space A so thatan SOION (SOI-on-nothing) substrate may be obtained, which is one typeof SOI substrate. The thermal oxidation layers 271 and 272 may act as apassivation layer for the active layer and the semiconductor substrate.

In addition, in accordance with above-mentioned embodiments of thepresent invention, the void space A between the substrate 200 and theactive layer 220 may be completely filled with the insulating layer 270during the process of forming the same.

Referring to FIGS. 6F, 7F, and 8E, the silicon nitride layer 240 and thepad oxidation layer 230 are removed to expose the active layer 220.

The thickness of the active layer may be reduced by forming and removingthe thermal oxidation layer on the active layer, and/or etching theactive layer.

Moreover, the process of patterning the sacrificial layer and the activelayer may be omitted in some embodiments of the present invention. Inother words, to obtain the structure as shown in FIGS. 6B, 7B, and 8A,an STI process may be performed to form the insulating layer 250 on thesubstrate 200 of the device isolation region I1. The sacrificial layer210 and the active layer 220 are then epitaxially grown on the exposedsubstrate 200 to have some sides of the sacrificial layer 210 and activelayer 220 contacting the insulating layer 250. Next, the pad oxidationlayer 230 and the silicon nitride layer 240 may be formed as apassivation layer on the sacrificial layer 220. Then, processes as shownin FIGS. 6C to 6E may be performed.

A process of forming a transistor may be performed after forming the SOIsubstrate in accordance with the above-mentioned embodiments of thepresent invention.

FIG. 9A shows a plan view for explaining methods for fabricatingsemiconductor devices in accordance with other embodiments of thepresent invention. In addition, FIGS. 9B and 9C show verticalcross-sectional views taken along lines V and VI of FIG. 9A,respectively.

Referring to FIGS. 9A to 9C, as shown in FIGS. 6F, 7F, and 8E of theabove-mentioned embodiments, an SOI substrate having a void space Abetween the substrate 200 and the active layer 220 is prepared. The voidspace A may be filled with an insulating layer. Alternatively, thermaloxidation layers may be formed on a lower surface of the active layer220 and on an upper surface of the substrate 200. A gate pattern G isthen formed on the active layer 220, wherein the gate pattern G includesa gate oxidation layer 281, a polysilicon layer 282, a silicide layer283 and a mask insulating layer 284, which are sequentially stacked. Aninsulating layer spacer 285 is then formed on a side of the gate patternG. A process of forming source/drain is performed. As shown in FIG. 9B,an epitaxial layer may be grown on the active layer 121 to form anelevated source/drain 286. Alternatively, the source/drain may be formedby implanting ions within the active layer 220 at both ends of the gatepattern G. Other conventional techniques may be used.

The gate pattern G may be formed within the active layer. Referring toFIG. 10, the SOI substrate having the void space A between the substrate200 and the active layer 220 is prepared, and the active layer 220 isselectively etched to form a trench (t) within the active layer 220. Thegate oxidation layer 281 is then formed on the active layer 220. Thetrench (t) is then filled with a conductive layer to form the gatepattern G. The source/drain 286 may be formed by implanting ions withinthe active layer 220 at both ends of the gate pattern G. Alternatively,the elevated source/drain may be formed as shown in FIG. 9B.

The gate pattern G may be formed by the process of forming and polishinga conductive layer on the active layer 220 or by the patterning process.The gate pattern G may be formed of a single layer or stacked layers.When the gate pattern G is formed of a polysilicon layer, a metal layermay be deposited and thermally treated on the polysilicon layer to forma self-aligned silicide layer.

SOI substrates fabricated by embodiments of the present invention may beused for a process of fabricating fin FET transistors.

FIGS. 11A to 11D show plan views for explaining methods for fabricatingsemiconductor devices in accordance with other embodiments of thepresent invention. FIGS. 12A to 12E show vertical cross-sectional viewstaken along line VII of FIGS. 11A, 11B, 11B, 11C, and 11D, respectively.FIGS. 13A to 13E show vertical cross-sectional views taken along lineVIII of FIGS. 11A, 11B, 11B, 11C, and 11D, respectively.

Referring to FIGS. 11A, 12A, and 13A, at least one stack pattern Siincluding a sacrificial layer 310, an active layer 320, a pad oxidationlayer 330 and a silicon nitride layer 340 is formed on a substrate 300such as a semiconductor substrate. Trenches (t1, t2) are formed on thesubstrate 300 as shown in FIGS. 11A and 12A while forming a plurality ofthe stack pattern S1. The trench t1 is formed within the substrate 300at both ends of the stack patterns S1, and the trench t2 is formedwithin the substrate 300 between the adjacent stack patterns S1.

An insulating layer 350 is formed to fill the trench t1 and extendedfrom the trench t1 to be in contact with all ends of the stack patternsS1. At the same time, an insulating layer 351 is also formed to fill thetrench t2 and portions between the adjacent stack patterns S1. Theseinsulating layers 350 and 351 may be formed of single layers, or a stacklayer formed of at least two kinds of insulating layers. The insulatinglayers 350 and 351 may act as first and second device isolation layers,respectively.

Referring to FIGS. 11B, 12B, and 13B, a mask 360 is formed to cover theinsulating layer 350. The insulating layer 351 is then removed at leastup to a height where the stack pattern S1 is exposed.

Referring to FIGS. 12C and 130, the sacrificial layer 310 is removed. Inthis case, the insulating layer 350 acts as a supporting layer that canprevent collapse of the active layer 320, the pad oxidation layer 330,and the silicon nitride layer 340. As the sacrificial layer 310 isremoved, some portions of the active layer 320, the pad oxidation 330,and the silicon nitride layer 340 remain to thereby form a stack patternS2.

An insulating layer 370 is then formed on the insulating layer 351 tofill a void space within the stack pattern S2. An insulating layer mayalso be formed between the substrate 300 and the active layer 320 tofill the void space during the process of forming the insulating layer370. Alternatively, oxidation layers may be formed on the upper surfaceof the substrate 300 and a lower surface of the active layer 320 duringthe process of forming the insulating layer 370 with the oxidationlayer.

Referring to FIGS. 11C, 12D, and 13D, after removing the insulatinglayer 370 until a side of the active layer 320 is exposed, the mask 360is removed. The silicon nitride layer 340 and the pad oxidation layer330 are then removed to expose an upper surface of the active layer 320.

Moreover, a thermal oxidation process as shown in FIGS. 5A to 5C may beperformed to form and remove a thermal oxidation layer (not shown) onthe upper surface and side of the active layer 320, so that thethickness and the width of the active layer 320 may be reduced.

Referring to FIGS. 11D, 12E, and 13E, a gate oxidation layer 381 and agate pattern G is formed to cover the upper surface and sides of theactive layer 320. Thus, a gate having a structure of triple fin FET isformed where a channel C1 is formed on the upper surface and both sidesof the active layer 320. An insulating layer spacer 383 is then formedon both sides of the gate pattern G. Source/drain 321 are then formed byimplanting ions within the active layer 320 at both ends of the gatepattern G.

Alternatively, during the process of forming the triple fin FET typegate, some portions of the silicon nitride layer and the pad oxidationlayer may remain on a lower portion of the gate to thereby form a dualfin FET type gate.

FIGS. 14A and 14B show plan views for explaining methods for fabricatingsemiconductor devices in accordance with other embodiments of thepresent invention. FIGS. 15A and 15B show vertical cross-sectional viewstaken along line VII of FIGS. 14A and 14B, respectively, and FIGS. 16Aand 16B show vertical cross-sectional views taken along line VIII ofFIGS. 14A and 14B, respectively.

First, as shown in FIGS. 12C and 13C, a sacrificial layer (not shown)between the substrate 300 and the active layer 320 is removed to form avoid space A in accordance with the above-mentioned embodiments of thepresent invention. As this void space A is formed, a plurality of stackpatterns S2 are formed to include the stacked active layer 320, and thepad oxidation layer 330 and the silicon nitride layer 340 on the activelayer 320. The insulating layer 370 fills between the stack patterns S2.The insulating layer 350 is in contact with the void space A and ends ofthe stack patterns S2.

Referring to FIGS. 14A, 15A, and 16A, the insulating layer 370 isremoved until sides of the active layer 320 are exposed. A conductivelayer 382 for a gate electrode and a gate oxidation layer 381 are formedon the silicon nitride 340, and a mask 400 is formed to define a gatepattern shape on the conductive layer 382.

Referring to FIGS. 14B, 15B, and 16B, the conductive layer 382, thesilicon nitride layer 340 and the pad oxidation layer 330 that are notcovered with the mask 400, are etched to form a gate pattern G, asilicon nitride layer 341 and a pad oxidation layer pattern 331, and themask 400 is removed. Thus, a transistor having a dual fin FET structureis formed where a channel C2 is formed on both sides of the active layer320.

Hereinafter, structural characteristics of semiconductor devices inaccordance with embodiments of the present invention will be described.

Referring to FIG. 9B, a semiconductor device in accordance with someembodiments of the present invention comprises a substrate 200 such assemiconductor substrate, an insulating layer 270 formed on the deviceisolation region of the substrate, and an active semiconductor layer 220having a lattice constant close to that of the substrate 200 and beingsupported by the insulating layer 270 and spaced from the substrate 200by a void space A therebetween. In addition, the semiconductor devicemay further comprise a gate pattern G stacked on the activesemiconductor layer 220. The gate pattern G may be formed of a gateoxidation layer 281, a polysilicon layer 282, a silicide layer 283, anda mask insulating layer 284, which are sequentially stacked on theactive layer 220. In addition, a semiconductor device in accordance withthe present invention may further comprise a source/drain 286 formed onthe active layer 220.

Referring to FIG. 10, the gate pattern G may be formed within the activesemiconductor layer 220. In addition, the source/drain 286 may be formedwithin the active semiconductor layer 220 at both ends of the gatepattern G.

Referring to FIG. 13E, a gate oxidation layer 381 and a gate pattern Gof the semiconductor device in accordance with embodiments of thepresent invention may cover the side and the upper surface of the activesemiconductor layer 320.

Referring to FIG. 16B, the upper surface of the active semiconductorlayer 320 is covered by the insulating layer, i.e., a pad oxidationlayer pattern 331 and a silicon nitride layer pattern 341, and bothsides of the active layer 320 may be in contact with a gate 380.

In accordance with some embodiments of the present invention, thesacrificial layer and the active semiconductor layer are epitaxiallygrown on a semiconductor substrate, and the sacrificial layer isselectively removed to thereby prepare an SOI substrate having theinsulating layer between the semiconductor substrate and the activelayer. In some embodiments, the active layer is epitaxially grown tofacilitate control of its thickness. In addition, since the processes ofbonding, isolating and polishing the active layer can be omitted, theactive layer does not need to be thickly formed and may not be consumed,and a thick active semiconductor layer does not need to be formed on awafer having a large diameter to thereby obtain the active layer havinga uniform thickness. Therefore, it is possible not only to mass-producethe semiconductor device using the SOI substrate fabricated byembodiments of the present invention, but also to potentially decreasethe manufacturing cost.

In the drawings and specification, there have been disclosed embodimentsof the invention and, although specific terms are employed, they areused in a generic and descriptive sense only and not for purposes oflimitation, the scope of the invention being set forth in the followingclaims.

1. A semiconductor device, comprising: a semiconductor substrate; adevice isolation layer on the semiconductor substrate; and an activesemiconductor layer spaced apart from the semiconductor substrate with avoid space interposed therebetween, supported by the device isolationlayer, and having a lattice constant close to that of the semiconductorsubstrate.
 2. The semiconductor device as claimed in claim 1, furthercomprising a gate electrode within the active layer or on the activelayer remote from the semiconductor substrate.
 3. The semiconductordevice as claimed in claim 2, wherein the gate electrode also extends ona side of the active semiconductor layer.
 4. The semiconductor device asclaimed in claim 3, wherein the gate electrode covers a surface of theactive semiconductor layer remote from the semiconductor substrate. 5.The semiconductor device as claimed in claim 1, further comprising: aninsulating layer on a surface of the substrate facing the activesemiconductor layer and on a surface of the active semiconductor layerfacing the substrate.
 6. The semiconductor device as claimed in claim 1,wherein the semiconductor substrate is a Si substrate, and the activesemiconductor layer is a Si epitaxial layer.